Low Power Explicit Pulsed Conditional Discharge Double Edge Triggered Flip-Flop

An explicit pulsed double edge triggered sense amplifier flip-flop for the low power and low delay is presented in this paper. The redundant transitions are eliminated by using the conditional technique named conditional discharge technique. By using the fast improved version of the nickolic latch along with the sense amplifier approach for the latching and the sensing stage the delay factor of the circuit is improved. Simulation using TSPICE and a 0.18μm CMOS technology shows that the proposed design has low power dissipation and small delay as compared to the existing design which use a conditional precharge technique in the design for removing the redundant transitions. Comparing with the previous work of the dual edge triggered flip-flops, the proposed one saved power upto 20.7%. The delay factor is improved by the factor of the 26.5% as compared to the existing design of the flip-flop.